engineering recuitment ISRO Scientist Computer Science Mock Test Computer Organization and Architecture Memory Management Associative Mapping
A certain processor uses a fully associative cache of size 32 kB. The cache block size is 32 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor?
1
27 bits and 5 bits
2
28 bits and 0 bits
3
28 bits and 5 bits
4
27 bits and 0 bits