engineering recuitment NIC NIELIT Scientist B 2023 Mock Test Computer Organization and Architecture Instruction Pipelining Instruction Pipeline
Consider the following processors. Assume that the pipeline registers have 2ns latency.
P1: Five-stage pipeline with stage latencies 3 ns, 2 ns, 6 ns, 2 ns, 1 ns.
P2: Six-stage pipeline with stage latencies 4 ns, 2ns, 5 ns, 1.5 ns, 3ns, 1ns.
P3: Four-stage pipeline with stage latencies 1 ns, 2 ns, 3 ns, 1 ns
P4: Six-stage pipeline with stage latencies 2 ns, 0.5 ns, 3 ns, 4 ns, 4 ns, 1ns.
P5: Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns
What is the highest clock frequency in MHz among the given processors?1
125
2
250
3
500
4
142