engineering recuitment NIC NIELIT Scientist B 2023 Mock Test Computer Organization and Architecture Memory Management Direct Mapping
A 128 KB direct mapped write back cache is organized as multiple blocks, each of size is 64 bytes. The processor generates 32 bit addresses. The cache controller maintains the tag information for each cache block comprising of 2 valid bit, 1 modified bit and 1 replacement bit. What is the total size of memory needed at the cache controller to store meta-data for the cache?
1
19 Kb
2
38 Kb
3
30 Kb
4
15 Kb