engineering recuitment UPMRC JE 2024 Mock Test Digital Electronics Sequential Circuits

A pulse train with a frequency of 1 MHz is counted using a mod-1024 ripple counter built with J-K flip-flops. For proper operation of the counter the maximum permissible propagation delay per flip-flop stage is

1

100 ns

2

50 ns

3

20 ns

4

10 ns

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