engineering recuitment GATE ECE 2023-24 Test Series Digital Electronics Combinational Circuits Adders
The propagation delay of AND gate is 1 nsec. Neglect the delay of H. A, the frequency of the input clock pulse is 250 MHz with a 50% duty cycle. The frequency (in MHz) of the pulse which is generated at Sum (S0) of Half Adder is _______.
Enter numerical value using the virtual keypad. Round off where necessary.