Parallel to-serial conversion can be done by means of shift register. Assume that a circuit accepts parallel data, B = b₇, b₆, ……, b₀, representing ASCII characters. Assume also that bit b₇ is set to 0. The circuit is supposed to generate a parity bit, p1 (based on odd parity logic) and send it instead of b₇ as a part of the serial transfer. Figure gives a possible circuit. An FSM is used to generate the parity bit, which is included in the output stream by using a multiplexer. A three-bit counter is used to determine when the p bit is transmitted, which happens when the count reaches 7. The desired FSM that performs the function is:

The correct FSM to implement the odd parity is