engineering recuitment GATE ECE 2023-24 Test Series Digital Electronics Combinational Circuits Multiplexer
The figure below shows a multiplexer where S1 and S0 are the select lines, I0 to I3 are the input data lines, EN is the enable line, and F(P, Q, R) is the output. F is
1
PQ + Q̅R
2
P + QR̅
3
PQ̅R + P̅Q
4
Q̅ + PR