engineering recuitment GATE ECE 2023-24 Test Series Digital Electronics Logic Gates and Boolean Algebra Logic Gates
For the logic diagram shown in figure (a), input waveform shown in figure (b) is applied at terminal A. If each gate has a propagation delay of 20 ns, the instant of time t (in ns) at which the output Y goes from logic 0 to logic 1 is _______.
Enter numerical value using the virtual keypad. Round off where necessary.