engineering recuitment GATE CSE 2023-24 Test Series Computer Organization and Architecture Instruction Pipelining Instruction Cycle
A certain processor deploys a single-level cache. The cache block size is 16 words and the word size is 4 bytes. The memory system uses a 100-MHz clock. To service a cache miss, the memory controller first takes 1 cycle to accept the starting address of the block, it then takes 5 cycles to fetch all the sixteen words of the block, and finally transmits the words of the requested block at the rate of 2 cycle per word. The maximum bandwidth for the memory system when the program running on the processor issues a series of read operations is ________× 107 bytes/sec.
Enter numerical value using the virtual keypad. Round off where necessary.