engineering recuitment GATE CSE 2023-24 Test Series Computer Organization and Architecture Machine Instructions and Addressing Modes Instruction Format
First field of the three field I.R. indicates op-code, second addresses a register from a set of 100 register and third is the memory address field.
A 32-bit instruction is placed in 1 MW memory.
If there are \(k\) instructions which uses both register and memory reference and \(l\) address register reference instructions then the number of zero address instructions possible are:1
\(\left[ {\left( {{2^5} - k} \right) \times {2^{20}} - l} \right] \times {2^7}\)
2
\(\left[ {\left( {{2^5} - k} \right) \times {2^7} - l} \right] \times {2^{20}}\)
3
\(\left[ {\left( {{2^5} - l} \right) \times {2^{20}} - k} \right] \times {2^7}\)
4
\(\left[ {\left( {{2^5} - l} \right) \times {2^7} - k} \right] \times {2^{20}}\)