engineering recuitment GATE CSE 2023-24 Test Series Computer Organization and Architecture Instruction Pipelining Instruction Pipeline
An instruction pipeline was designed with five stages. latency of each of the stage will be 40 ns, 20 ns, 25 ns, 50 ns, and 10 ns. The pipeline latch latency is 5 ns. Which of the following cannot be the cycle time of the pipeline?
1
55 ns
2
45 ns
3
25 ns
4
30 ns