engineering recuitment GATE CSE 2023-24 Test Series Computer Organization and Architecture Memory Management Set Associative Mapping
Consider two cache organization which are byte addressable. In both cache organization cache size is 64 KB with 32 - byte block. The first cache organization is direct mapped while the other is 4 way set associative. Physical address is of size 32 bit in both the organization. K - bit comparator has a latency of (k × 0.5) ns and latency of OR gate is 1 ns. Find sum the latency of the direct mapped organization and set associative organization?
1
16 ns
2
17 ns
3
18 ns
4
19 ns