engineering recuitment GATE CSE 2023-24 Test Series Computer Organization and Architecture Instruction Pipelining Instruction Pipeline
Consider a non-pipelined processor with a clock rate of 2.5 GHz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 GHz. Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor is
1
3.2
2
3.0
3
2.2
4
2.0