engineering recuitment GATE CSE 2023-24 Test Series Computer Organization and Architecture Data-Path and Control Unit Single Bus Organization
Consider a memory unit of size 96 K × 16, where first component represents the number of words and that the second component represents the number of bits per word. What will be the number of address lines and input-output data lines?
1
16 address lines, 17 data lines
2
7 address lines, 16 data lines
3
17 address lines, 16 data lines
4
16 address lines, 7 data lines