engineering recuitment GATE CSE 2023-24 Test Series Computer Organization and Architecture Instruction Pipelining Instruction Pipeline
Consider the following processors. Assume that the pipeline registers have 0 latency.
P1: Five-stage pipeline with stage latencies 3 ns, 2 ns, 4 ns, 2 ns, 1ns.
P2: Six-stage pipeline with stage latencies 4 ns, 3ns, 5 ns, 1.5 ns, 2ns, 0.5ns.
P3: Four-stage pipeline with stage latencies 1 ns, 2 ns, 3 ns, 1 ns
P4: Four-stage pipeline with stage latencies 2 ns, 3 ns, 4 ns, 1 ns
Which processor has the highest clock frequency?1
P1
2
P2
3
P3
4
P4