engineering recuitment GATE CSE 2023-24 Test Series Computer Organization and Architecture I/O Interface Interrupt Request Lines
In processor P , non preemptive priority interrupts 4 , 7 , 1 , 3 , 0 , 2 , 6 arrive sequentially (low number high priority) . If when one interrupt is being handled exactly two more interrupts arrive. What is order of these interrupts handled by P :
1
4, 7, 1, 3, 0, 2, 6
2
4, 1, 3, 0, 2, 6, 7
3
0, 1, 2, 3, 4, 6, 7
4
4, 1, 0, 2, 3, 6, 7