engineering recuitment HPCL Junior Executive 2025 Mock Test Digital Electronics Logic Gates and Boolean Algebra Logic Gates
For the gates shown in Fig. (a) and Fig. (b), the x and y inputs are respectively,
1
0 and 0
2
0 and 1
3
1 and 0
4
1 and 1
For the gates shown in Fig. (a) and Fig. (b), the x and y inputs are respectively,