engineering recuitment HPCL Junior Executive 2025 Mock Test Digital Logic Combinational Circuits Multiplexer
A 4 × 1 Multiplexer is shown in the Figure below. The output Z is
1
A NOR C
2
B NOR C
3
B XOR C
4
A XOR C
A 4 × 1 Multiplexer is shown in the Figure below. The output Z is