railway DFCCIL Executive 2025 Mock Test Digital Logic Combinational Circuits Adder

The carry expression for a 3-bit full adder having input X, Y, Z is:

1
C = X.Y + ( X ⊕ Y ) Z
2
C = Y.Z + ( X ⊕ Y ) Z
3
C = X.Z + ( X ⊕ Y ) Z
4
C = X.Y + ( X ⊙ Y ) Z
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