railway RRB JE (CBT I + CBT II) Mock Test 2024 Digital Logic Sequential Circuits Counter

A 4-bit modulo 16 ripple counter uses JK flip flop. If the propagation delay of each flip flop is 50 ns, The maximum clock frequency that can be used is

1

20 MHz

2

10 MHz

3

5 MHz

4

4 MHz

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