Which logic inputs should be given to the input lines I0, I1, I2 and I3, if the MUX is to behave as two input XNOR gate?
1
0110
2
1001
3
1010
4
1111
Which logic inputs should be given to the input lines I0, I1, I2 and I3, if the MUX is to behave as two input XNOR gate?