Teaching HPSC Lecturer (Technical) Mock Test 2024 Computer Organization and Architecture Instruction Pipelining Instruction Pipeline
We have two designs D1 and D2 for a synchronous pipeline processor. D1 has 5 pipeline stages with execution times of 3 nsec, 2 nsec, 4 nsec, 2 nsec and 3 nsec while the design D2 has 8 pipeline stages each with 2 nsec execution time. How much time can be saved using design D2 over design D1 for executing 100 instructions?
1
214 nsec
2
202 nsec
3
86 nsec
4
–200 nsec
5
Question Not Attempted