The logic levels H and L at different locations in a digital circuit are found to be as shown in the figure.
Based on these observations, which of the logic gates is not behaving as an ideal NAND gate?
1
G2
2
G3
3
G4
4
G1
The logic levels H and L at different locations in a digital circuit are found to be as shown in the figure.
Based on these observations, which of the logic gates is not behaving as an ideal NAND gate?