Teaching UGC NET Mock Test Series 2025 (Paper 1 & 2) Computer Organization and Architecture Instruction Pipelining Synchronous Pipelines
A 4-stage pipeline has the stage delay as 150, 120, 160 and 140 ns respectively. Registers that are used between the stages have delay of 5 ns. Assuming constant locking rate, the total time required to process 1000 data items on this pipeline is
1
160.5 ms
2
165.5 ms
3
120.5 ms
4
590.5 ms