Consider the following VHDL code. What does it represent?

process

begin

CLK <= '0' ;

wait for 20 ns;

CLK <= '1' ;

wait for 12 ns;

end process;

1
A clock with on time of 20 ns
2
A clock with the on-time of 12 ns
3
A clock with the off time of 12 ns
4
This is not related to clock generation

Sponsored

hivanix.in

Visit

This quiz is brought to you by hivanix.in

🌐 Web App Development

Quick Navigation