engineering recuitment ISRO Scientist Electronics Mock Test Control Systems Time Response Analysis Steady State Error
A closed loop system is shown in the figure where k > 0 and α > 0. The steady state error due to a ramp input (R(s) = α/s2) is given by
1
\(\rm \frac{2\alpha}{k}\)
2
\(\rm \frac{\alpha}{k}\)
3
\(\rm \frac{\alpha}{2k}\)
4
\(\rm \frac{\alpha}{4k}\)