engineering recuitment GATE IN Test Series 2023-24 Mock Test Communication Systems Receivers FM Receivers
The block diagram of a frequency synthesizer consisting of a Phase Locked Loop (PLL) and a divide-by-๐ counter (comprising รท 2 ,รท 4, รท 8, รท 16 outputs) is sketched below. The synthesizer is excited with a 5 kHz signal (Input 1). The free-running frequency of the PLL is set to 20 kHz. Assume that the commutator switch makes contacts repeatedly in the order 1-2-3-4.
The corresponding frequencies synthesized are:
1
10 kHz, 20 kHz, 40 kHz, 80 kHz
2
20 kHz, 40 kHz, 80 kHz, 160 kHz
3
80 kHz, 40 kHz, 20 kHz, 10 kHz
4
160 kHz, 80 kHz, 40 kHz, 20 kHz