engineering recuitment GATE IN Test Series 2023-24 Mock Test Digital Electronics Sequential Circuits Shift Register Counters
Consider the Johnson counter and the clock timing diagram as shown in the figure below. Let the initial state of Johnson counter be 0000. Consider the delay from i/p to o/p of each flip flop is 0.1 ns. After how much time of the counter will be all zero again?
1
8 ms
2
13 ms
3
15 ms
4
16 ms