engineering recuitment GATE EE 2023-24 Test Series Digital Electronics Combinational Circuits Realization of Logic Gates
Consider the logic diagram below:
Suppose the circuit takes BCD only inputs i.e. 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001 and generate a logic HIGH output (F = 1) only when any two inputs are logic HIGH, (consider the invalid combinations for BCD input to be don’t care condition).
The correct SOP expression for output F is
1
A C̅ D + B C̅ D + B̅ C D + B C D̅
2
A̅ C D + B C̅ D + B̅ C D + B C D̅
3
A C + B C̅ D + B C D̅ + B̅ C D
4
AD + B C̅ D + B C D̅ + B̅ C D