Consider a 4-bit counter constructed out of four flipflops. It is formed by connecting the J and K inputs to logic high and feeding the Q output to the clock input of the following flip-flop (see the figure). The input signal to the counter is a series of square pulses and the change of state is triggered by the falling edge. At time t = t₀ the outputs are in logic low state (Q₀ = Q₁ = Q₂ = Q₃ = 0). Then at t = t₁, the logic state of the output is