Consider the logic circuit given below:
The current state QA QB of a two JK flip flop system is 00.
Which of the following is/are true?
1
The modulus of the counter is 5
2
The state of QA QB after first clock pulse is 11.
3
The state of QA QB after 100th clock pulse is 00.
4
For input frequency of 10 kHz, the output frequency will be 2 kHz.