engineering recuitment GATE EE 2023-24 Test Series Digital Electronics Combinational Circuits Decoders
The following switching functions are to be implemented using a Decoder.
\({F_1} = \sum m\left( {1,2,4,8,10,14} \right)\)
\({F_2} = \sum m\left( {2,5,9,11} \right)\)
\({F_2} = \sum m\left( {2,4,5,6,7} \right)\)
The minimum configuration of the decoder should be
1
2 – to – 4 line
2
3 – to – 8 line
3
4 – to – 16 line
4
5 – to – 32 line