engineering recuitment GATE EE 2023-24 Test Series Digital Electronics Sequential Circuits Asynchronous Counters
The propagation delay of the exclusive-OR (XOR) gate in the circuit in the figure is 3 ns. The propagation delay of all the flip-flops is assumed to be zero. The clock (Clk) frequency provided to the circuit is 500 MHz.
Starting from the initial value of the flip-flop outputs Q2 Q1 Q0 = 1 1 1 with D2 = 1, then the minimum number of triggering clock edges after which the flip-flop outputs Q2 Q1 Q0 becomes 1 0 0 (in integer) is ______
Enter numerical value using the virtual keypad. Round off where necessary.