In the sequential circuit below, the minimum clock period to avoid setup time violation (Assume clock is perfectly synchronized, i.e. no clock skew)
1
Period ≥ (max FF prop. Delay) + (max comb-circuit delay)
2
Period ≥ (max FF prop. Delay) + min comb-circuit delay) + (FF setup time)
3
Period ≥ (min FF prop-delay) (min comb circuit delay) + (FF setup time)
4
Period ≥ (max FF prop. Delay) + (max comb. Circuit delay) + (FF setup time)