engineering recuitment GATE ECE 2023-24 Test Series Network Theory Sinusoidal Steady State Analysis Sinusoidal Response of Parallel RL Circuit
Consider the following statements for the circuit shown in the figure:
Which of the above statements is/are correct
1
The current in the circuit lags the source voltage by 63.43°
2
The current in the circuit lags the source voltage by 26.57°
3
The voltage across the inductor lags the source voltage by 90°
4
The voltage across the inductor leads the source voltage by 63.43°