engineering recuitment GATE ECE 2023-24 Test Series Digital Electronics Sequential Circuits Memory Elements
A finite state machine (FSM) is implemented using the D flip-flops A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are QAQB = 00,01,10, and 11.
Assume that XIN is held at a constant logic level throughout the operation of the FSM. When the FSM is initialized to the state QAQB = 00 and clocked, after a few clock cycles, it starts cycling through
1
all of the four possible states if XIN = 1
2
three of the four possible states if XIN = 0
3
only two of the four possible states if XIN = 1
4
only two of the four possible states if XIN = 0