engineering recuitment GATE ECE 2023-24 Test Series Digital Electronics Logic Gates and Boolean Algebra Logic Gates
In the circuit shown, the switch is momentarily closed and then opened. Assuming the logic gates to have equal non-zero delay, at steady state, the logic states of X and Y are
1
X is latched, Y toggles continuously
2
X and Y are both latched
3
Y is latched, X toggles continuously
4
X and Y both toggle continuously