engineering recuitment GATE ECE 2023-24 Test Series Digital Electronics Combinational Circuits Realization of Logic Gates
Consider the logic circuit with input signal TEST shown in the figure. All gates in the figure shown have identical non-zero delay. The signal TEST which was at logic LOW is switched to logic HIGH and maintained at logic HIGH. The output
1
stays HIGH throughout
2
stays LOW throughout
3
pulses from LOW to HIGH to LOW
4
pulses from HIGH to LOW to HIGH