engineering recuitment GATE ECE 2023-24 Test Series Control Systems Time Response Analysis Steady State Error
The steady-state error for a Type 0 system for unit-step input is 0.2. In a certain instance, this error possibility was removed by the insertion of a unity gain block. Thereafter, a unit ramp was applied. The nature of the block and new steady-state error in this changed configuration will, respectively, be
1
integrator, 0.25
2
differentiator, 0.25
3
integrator, 0.20
4
differentiator, 0.20