engineering recuitment GATE ECE 2023-24 Test Series Digital Electronics Logic Gates and Boolean Algebra Logic Gates
Assume that the logic gates given in Fig. A) have zero propagation delay and SW1 is initially closed. The waveform applied at terminal A is as shown in Fig. B). If switch SW1 is opened at t = 30 ns, then the total duration for which output terminal (x) will be at logic high is __________ (in ns).
Enter numerical value using the virtual keypad. Round off where necessary.