Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor R = 10 kΩ and the supply voltage is 5 V. The D flip flops D₁, D₂, D₃, D₄ and D₅ are initialised with logic values 0101 and 0 respectively.

Consider two cases

Case a: Clock of 30% duty cycle is applied and average power dissipated is P₁ mW in resistor R

Case b: Clock of 50% duty cycle is applied and average power dissipated is P₂ mW in resistor R

Then which of the following statement is true