engineering recuitment GATE CSE 2023-24 Test Series Digital Electronics Sequential Circuits Memory Elements
Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop.
Which of the following is/are correct about the output of the above circuit?
Before the 1st clock, both Q0 and Q1 are set to 1.
1
Q1 Q0 after the 1st cycle are 01
2
Q1 Q0 after the 3rd cycle are 11
3
Q1 Q0 after the 4th cycle are 01
4
Q1 Q0 after the 2nd cycle are 10