engineering recuitment GATE CSE 2023-24 Test Series Computer Organization and Architecture Memory Management Memory Hierarchy
A reference to the instruction cache is implied by each instruction fetch, and 20% of all instructions make use of data memory.
Implementation of the cache is as follows:
L1 data and instruction caches are directly linked to the CPU.
The L1 instruction cache has an average miss rate of 5%.
In the L1 data cache, the average miss rate was 15%.
The missed penalty in both situations is 10 clock cycles.
What is the overall miss penalty in clock cycles?
Enter numerical value using the virtual keypad. Round off where necessary.