engineering recuitment GATE CSE 2023-24 Test Series Computer Organization and Architecture Instruction Pipelining
Consider a 5-stage pipeline having stages as Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX) and Write Back (WB). Here we are given 4 instructions. IF, ID, OF and WB stages take 1 clock cycle each, but the EX-stage takes 1 cycle for ADD and SUB, 2 cycles for MUL and 3 cycles for DIV operation. If the operand forwarding technique is used from EX stage to OF stage and the clock rate of pipeline processor is 5 GHz, then choose the correct statement(s), considering the below table:
| Instruction Number | Instruction | Meaning |
| I1 | DIV R1, R2 R3 | \(R1\, ← \frac{{R2}}{{R3}}\) |
| I2 | MUL R6, R5, R4 | R6 ← R5 × R4 |
| I3 | SUB R0, R1, R6 | R0 ← R1 - R6 |
| I4 | ADD R8, R0, R7 | R8 ← R0 + R7 |
1
The instruction I3 gets executed in the 10th clock cycle.
2
Number of True dependencies are 3.
3
Total number of clock cycles required are 11.
4
Total execution time is 2200 picoseconds.