Consider a 2–way set associative cache with 128 blocks and uses LRU replacement. Initially, the cache is empty. Conflict misses occur when two or more blocks contend for the same cache set. First reference misses access due to first time block access. The memory access sequence:

(0, 64, 128, 64, 0, 64, 128, 64, 1, 65, 129, 65, 1, 65, 129, 65)

is repeated 2 times. The number of conflict misses and miss ratio in the cache are ______.