engineering recuitment GATE CSE 2023-24 Test Series Computer Organization and Architecture Instruction Pipelining Instruction Cycle
Consider an instruction pipeline having 5 stages:
IF = Instruction Fetch stage
ID = Instruction Decode stage
OF = Operand Fetch stage
EX = Execute stage
WB = Write Back stage
Now consider the following instructions:
| I1 : ADD | R1, R9, R10 | R1← R9 + R10 |
| I2 : DIV | R4, R2, R3 | \(R4\leftarrow \frac{R2}{R3} \) |
| I3 : MUL | R5, R4, R1 | R5← R4× R1 |
| I4 : ADD | R6, R4, R5 | R6 ← R4 + R5 |
| I5 : SUB | R8, R6, R7 | R8← R6 - R7 |
Each stage takes 1 clock cycle for all the instructions. If x is the number of clock cycles required without operand forwarding and y is the number of clock cycles required with operand forwarding, then find the value of x/y (Corrected up to 2 decimal places). Here operand is forwarded from EX stage to OF stage.
Enter numerical value using the virtual keypad. Round off where necessary.