engineering recuitment GATE CSE 2023-24 Test Series Computer Organization and Architecture Instruction Pipelining Instruction Pipeline
Consider the following processor (ns stands for nanoseconds). Assume that the pipeline registers have zero latency.
P1: Four-stage pipeline with stage latencies 2 ns, 3 ns, 3 ns, 2 ns.
P2: Four-stage pipeline with stage latencies 2 ns, 2.5 ns, 2.5 ns, 2.5 ns.
P3: Five-stage pipeline with stage latencies 1 ns, 2 ns, 3 ns, 1.2 ns, 2 ns
P4: Five-stage pipeline with stage latencies 1.5 ns, 1.5 ns, 2 ns, 1 ns, 2 ns
Which processor has the lowest peak clock frequency?
1
P4
2
P3
3
P2
4
P1