The latencies for each stage in a single cycle processor is given as
|
IF |
ID |
ALU |
MEM |
WB |
|
20ns |
25ns |
40ns |
40ns |
5ns |
Further assume there is a buffer delay of 5ns at each stage if pipelining is implemented.
The speedup obtained from pipelining is ____
Enter numerical value using the virtual keypad. Round off where necessary.