Consider a 5-stage pipeline with stage delays 8 ns, 2 ns, 12 ns, 15 ns, 9 ns. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2.5 ns. The speedup factor achieved by pipeline implementation over non – pipeline implementation is 1.05. Average execution time for non-pipeline implementation is 1911 ns. Find the number of instructions.