Consider a non-pipelined processor with a clock rate of 5 GHz and average cycle per instruction of 6. The same processor is upgraded to a pipeline with 4 stages but due to the internal pipeline delay, the clock speed is reduced to 2 GHz. Assume that there are no stalls in the pipeline. What is the speed up of the pipeline in steady state under ideal conditions when compared to the corresponding non-pipeline implementation (answer up to 1 decimal place)?